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dual-channel, 14-bit ccd signal processor with precision timing ? core ad9942 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 40 mhz correlated double sampler (cds) 0 db to 18 db, 9-bit variable gain amplifier (vga) 40 msps analog-to-digital converter (adc) optical black clamp (clpob) with variable level control complete on-chip timing driver precision timing core with <550 ps resolution on-chip 3 v horizontal and rg drivers 4-phase h-clock mode 100-lead, 9 mm 9 mm, csp_bga package applications signal processor for dual-channel ccd outputs digital still cameras digital video cameras high speed digital imaging applications general description the ad9942 is a highly integrated dual-channel ccd signal processor for digital still camera applications. each channel is specified at pixel rates of up to 40 mhz. the ad9942 consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver. the precision timing core allows high speed clocks to be adjusted with 550 ps resolution. the analog front end uses black level clamping and includes a vga, a 40 msps adc, and a cds. the timing driver provides the high speed ccd clock drivers for rg_a and rg_b, as well as the h1a to h4a and h1b to h4b outputs. the 6-wire serial interface is used to program the ad9942. available in a space-saving, 9 mm 9 mm, csp_bga package, the ad9942 is specified over an operating temperature range of ?25c to +85c. functional block diagram 05240-001 ad9942 sync generator precision timing core internal clocks horizontal drivers rg_b rg_a h1a to h4a 4 h1b to h4b 4 hd_a vd_a hd_b vd_b internal registers sl_a sdata_a sl_b sdata_b sck_a sck_b cli_a cli_b clamp dout_a ccdin_a 0db ~ 18db vga adc cds 14 clamp dout_b ccdin_b 0db ~ 18db vga adc cds 14 reft_b refb_b vref_b reft_ a refb_ a vref_a figure 1.
ad9942 rev. a | page 2 of 36 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 general specifications ................................................................. 3 digital specifications ................................................................... 4 analog specifications................................................................... 5 channel-to-channel specifications........................................... 6 timing specifications .................................................................. 7 absolute maximum ratings............................................................ 8 thermal resistance ...................................................................... 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 terminology .................................................................................... 11 equivalent input/output circuits ................................................ 12 typical performance characteristics ........................................... 13 system overview ............................................................................ 14 serial interface timing .................................................................. 15 complete register listing ......................................................... 16 channel a and channel b precision timing ............................... 19 high speed timing generation ............................................... 19 timing resolution...................................................................... 19 high speed clock programmability........................................ 19 h driver and rg outputs......................................................... 21 digital data outputs.................................................................. 21 channel a and channel b horizontal clamping and blanking ....22 individual clpob and pblk sequences................................ 22 individual hblk sequences..................................................... 22 channel a and channel b special hblk patterns.................... 24 horizontal sequence control ................................................... 24 h-counter synchronization ..................................................... 25 channel a and channel b power-up procedure....................... 26 channel a and channel b analog front end operation......... 27 dc restore .................................................................................. 27 correlated double sampler ...................................................... 27 channel a and channel b variable gain amplifier ............. 28 channel a and channel b adc .............................................. 28 channel a and channel b clpob.......................................... 28 channel a and channel b digital data outputs................... 28 applications information .............................................................. 29 circuit configuration ................................................................ 29 grounding/decoupling recommendations ........................... 29 driving the cli input................................................................ 31 horizontal timing sequence example.................................... 31 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 33 revision history 8/06rev. 0 to rev. a changes to table 3............................................................................ 5 changes to table 13........................................................................ 17 change to channel a and channel b variable gain amplifier section............................................... 28 updated outline dimensions ....................................................... 33 1/05revision 0: initial version
ad9942 rev. a | page 3 of 36 specifications general specifications x = a, b. table 1. parameter min typ max unit temperature range operating ?25 +85 c storage ?65 +150 c maximum clock rate 40 mhz power supply voltage avdd_x, tcvdd_x (afe, timing core) 2.7 3.0 3.6 v hvdd_x (h1x to h4x drivers) 2.7 3.0 3.6 v rgvdd_x (rg_x driver) 2.7 3.0 3.6 v drvdd_x (d0 to d13 drivers) 2.7 3.0 3.6 v dvdd_x (digital) 2.7 3.0 3.6 v power dissipation for each channel (40 mhz, 3 v supplies, 100 pf h1x to h4x loading, 10 pf rg_x loading) power from avdd_x 110 mw power from tcvdd_x 33 mw power from hvdd_x 1 160 mw power from rgvdd_x 13 mw power from drvdd_x 15 mw power from dvdd_x 40 mw total shutdown mode 2 mw 1 total hvdd_x power = [(c load ) (hvdd_x) (pixel frequency)] (hvdd_x) (number of horizontal outputs used).
ad9942 rev. a | page 4 of 36 digital specifications t min to t max , avdd_x = dvdd_x = drvdd_x = hvdd_x = rgvdd_x = 2.7 v, c l = 20 pf, unless otherwise noted. x = a, b. table 2. parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v cli input high level input voltage (tcvdd_x/2 + 0.5 v) v ih ? cli 1.85 v low level input voltage v il ? cli 0.85 v rg_x and h1x to h4x driver outputs high level output voltage (rgvdd_x C 0.5 v and hvdd_x C 0.5 v) v oh 2.2 v low level output voltage v ol 0.5 v maximum output current (programmable) 30 ma maximum load capacitance 100 pf
ad9942 rev. a | page 5 of 36 analog specifications t min to t max , avdd_x = dvdd_x = 3.0 v, f cli = 40 mhz, typical timing specifications, unless otherwise noted. x = a, b. table 3. parameter min typ max unit notes cds gain 0 db allowable ccd reset transient 1 500 mv max input range before saturation 1.0 v p-p max ccd black pixel amplitude 100 mv measured at 12 db vga gain (typ = 70 mv at 15 db and 50 mv at 18 db) variable gain amplifier (vga_x) max input range 1.0 v p-p max output range 2.0 v p-p gain control resolution 512 steps gain monotonicity guaranteed gain range min gain (code 0) 0 db max gain (code 511) 18 db clpob clamp level resolution 256 steps 4 lsb/step clamp level measured at adc output min clamp level 0 lsb max clamp level 1023 lsb chn_a and chn_b adc differential nonlinearity (dnl) ?1.0 0.5 +1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (reft_x) 2.0 v reference bottom voltage (refb_x) 1.0 v system performance specifications include entire signal chain vga gain accuracy min gain (code 0) ?0.5 0 +0.5 db max gain (code 511) 17.5 18 18.5 db peak nonlinearity, 500 mv input signal 0.15 % 12 db gain applied total output noise 3 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 50 db measured with step change on supply 1 input signal characteristics defined as follows: 0 5240-099 100mv max optical black pixel 500mv typ reset transient 1v max input signal range
ad9942 rev. a | page 6 of 36 channel-to-channel specifications t min to t max , avdd_x = dvdd_x = 3.0 v, f cli = 40 mhz, typical timing specifications, unless otherwise noted. x = a, b. table 4. parameter min typ max unit notes channel a/channel b output code matching error 1 <1.0% vga = 6 db, 12 db, and 18 db conditions. crosstalk error vga = 6 db, 12 db, and 18 db conditions. channel a to channel b ?84 db full-scale step applied to channel a while measuring response on channel b. channel b to channel a ?84 db full-scale step applied to channel b while measuring response on channel a. 1 matching error calculated using a ramp input applied to channel a and channel b simultaneously. typical channel a/channel b er ror is <1.0% at each output code.
ad9942 rev. a | page 7 of 36 timing specifications c l = 20 pf, f cli = 40 mhz, serial timing in figure 14 and figure 15 , unless otherwise noted. x = a, b. table 5. parameter symbol min typ max unit master clock (cli_x) (see figure 16 ) cli_x clock period 25.0 ns cli_x high/low pulse width t adc 10.0 12.5 15.0 ns delay from cli_x to internal pixel period position (see figure 16 ) t clidly 6 ns clpob_x pulse width (programmable) 1 t cob 2 20 pixels sample clocks (see figure 17 ) shp_x rising edge to shd_x rising edge t s1 11.2 12.5 ns data outputs (see figure 19 and figure 20 ) output delay from programmed edge t od 6 ns pipeline delay 11 cycles serial interface maximum sck_x frequency f sclk 10 mhz sl_x to sck_x setup time t ls 10 ns sck to sl_x hold time t lh 10 ns sdata_x valid to sck_x rising edge setup t ds 10 ns sck_x falling edge to sdata_x valid hold t dh 10 ns sck_x falling edge to sdata_x valid read t dv 10 ns 1 minimum clpob pulse width is for functional operation only. wi der typical pulses are recommended to achieve low noise clamp re ference.
ad9942 rev. a | page 8 of 36 absolute maximum ratings table 6. ratings (x = a, b) parameter rating avdd_x and tcvdd_x to avss_x ?0.3 v to +3.9 v hvdd_x and rgvdd_x to hvss_x and rgvss_x ?0.3 v to +3.9 v dvdd_x and drvdd_x to dvss_x and drvss_x ?0.3 v to +3.9 v any vss_x to any vss_x ?0.3 v to +0.3 v digital outputs to drvss_x ?0.3 v to drvdd + 0.3 v sck_x, sl_x, and sdata_x to dvss_x ?0.3 v to dvdd + 0.3 v rg_x to rgvss_x ?0.3 v to rgvdd + 0.3 v h1x to h4x to hvss_x ?0.3 v to hvdd + 0.3 v reft_x, refb_x, and ccdin_x to avss_x ?0.3 v to avdd + 0.3 v junction temperature 150c lead temperature (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance 100-lead, 9 mm 9 mm, csp_bga package: ja = 38.3c/w 1 1 ja is measured using a 4-layer pcb with the exposed paddle soldered to the board. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9942 rev. a | page 9 of 36 pin configuration and fu nction descriptions 05240-002 1 a1 corne r index are a 2345678910 a b c d e f g h j k ad9942 top view (not to scale) figure 2. pin configuration table 7. pin function descriptions ball location mnemonic type 1 description b2 sl_a di 6-wire serial load for channel a c2 sdata_a di 6-wire serial data for channel a d2 sck_a di 6-wire serial clock for channel a c1 reft_a ao reference top decoupling for channel a (decouple with 1.0 f to avss_a) d1 refb_a ao reference bottom decoupling fo r channel a (decouple with 1.0 f to avss_a) a1 ccdin_a ai analog input for channel a ccd sign al (connect through series 0.1 f capacitor) f4 h1a do ccd horizontal clock 1 for channel a f3 h2a do ccd horizontal clock 2 for channel a d4 h3a do ccd horizontal clock 3 for channel a d3 h4a do ccd horizontal clock 4 for channel a b4 rg_a do ccd reset gate clock for channel a j2 drvss_a p digital driver ground for channel a k3 drvdd_a p digital driver supply for channel a e3 hvss_a p h1a to h4a driver ground for channel a e4 hvdd_a p h1a to h4a driver supply for channel a c3 rgvss_a p rg_a driver ground for channel a c4 rgvdd_a p rg_a driver supply for channel a b3 tcvss_a p analog ground for channel a timing core a4 tcvdd_a p analog supply for channel a timing core b1 avss_a p analog ground for channel a a2 avdd_a p analog ground for channel a f2 dvss_a p digital ground for channel a f1 dvdd_a p digital supply for channel a e2 vd_a di vertical sync pulse for channel a e1 hd_a di horizontal sync pulse for channel a b8 sl_b di 6-wire serial load for channel b c8 sdata_b di 6-wire serial data for channel b d8 sck_b di 6-wire serial clock for channel b c7 reft_b ao reference top decoupling for channel b (decouple with 1.0 f to avss_b) d7 refb_b ao reference bottom decoupling fo r channel b (decouple with 1.0 f to avss_b) a7 ccdin_b ai analog input for channel b ccd sign al (connect through series 0.1 f capacitor) f10 h1b do ccd horizontal clock 1 for channel b f9 h2b do ccd horizontal clock 2 for channel b d10 h3b do ccd horizontal clock 3 for channel b
ad9942 rev. a | page 10 of 36 ball location mnemonic type 1 description d9 h4b do ccd horizontal clock 4 for channel b b10 rg_b do ccd reset gate clock for channel b j8 drvss_b p digital driver ground for channel b k9 drvdd_b p digital driver supply for channel b e9 hvss_b p h1b to h4b driver ground for channel b e10 hvdd_b p h1b to h4b driver supply for channel b c9 rgvss_b p rg_b driver ground for channel b c10 rgvdd_b p rg_b driver supply for channel b b9 tcvss_b p analog ground for channel b timing core a10 tcvdd_b p analog supply for channel b timing core b7 avss_b p analog ground for channel b a8 avdd_b p analog ground for channel b f8 dvss_b p digital ground for channel b f7 dvdd_b p digital supply for channel b e8 vd_b di vertical sync pulse for channel b e7 hd_b di horizontal sync pulse for channel b a3 cli_a di master clock input for channel a g1 d0_a do data output channel a h1 d1_a do data output channel a j1 d2_a do data output channel a k1 d3_a do data output channel a g2 d4_a do data output channel a h2 d5_a do data output channel a k2 d6_a do data output channel a g3 d7_a do data output channel a h3 d8_a do data output channel a j3 d9_a do data output channel a k4 d10_a do data output channel a j4 d11_a do data output channel a h4 d12_a do data output channel a g4 d13_a do data output channel a a5, b5, c5, d5, e5, f5, g5, h5, j5, k5, a6, b6, c6, d6, e6, f6, g6, h6, j6, k6 gnd p ground connection a9 cli_b di master clock input for channel b g7 d0_b do data output channel b h7 d1_b do data output channel b j7 d2_b do data output channel b k7 d3_b do data output channel b g8 d4_b do data output channel b h8 d5_b do data output channel b k8 d6_b do data output channel b g9 d7_b do data output channel b h9 d8_b do data output channel b j9 d9_b do data output channel b k10 d10_b do data output channel b j10 d11_b do data output channel b h10 d12_b do data output channel b g10 d13_b do data output channel b 1 ai = analog input, ao = analog output, di = digital input, do = digital output, p = power.
ad9942 rev. a | page 11 of 36 terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. therefore, every code must have a finite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ad9942 from a true straight line. the point used as zero scale occurs 0.5 lsb before the first code transition. positive full scale is defined as a level 1 lsb and 0.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percentage of the 2 v adc full-scale signal. the input signal is always appropriately gained up to fill the adcs full-scale range. tot a l o utput noi s e the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be converted to an equivalent voltage, using the relationship 1 lsb = ( adc full scale /2 n codes ) where n is the bit resolution of the adc. for the ad9942, 1 lsb is approximately 122.0 v. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage. matching error the matching error refers to the channel a to channel b mismatch after post-adc correction calibration has been applied to remove gain error between channel a and channel b. crosstalk the crosstalk is measured while applying a full-scale step to one channel and measuring the interference on the opposite channel. ? ? ? ? ? ? ? ? = 384,16 )( log20)db( lsbceinterferen crosstalk
ad9942 rev. a | page 12 of 36 equivalent input/output circuits x = a, b. r avdd avss avss 05240-003 figure 3. ccdin_x a v dd avss 330? cli 25k ? 1.4v 05240-004 + figure 4. cli_x dvss drvdd dvss drvss data three-state dout 05240-005 figure 5. data outputs d0_x to d13_x 05240-006 dvdd dvss 330 ? figure 6. digital inputs 05240-007 hvdd or rgvdd hvss or rgvss data enable dout figure 7. h1x to h4x and rg_x
ad9942 rev. a | page 13 of 36 typical performance characteristics 1.0 0.5 0 ?0.5 ?1.0 0 4000 8000 12000 16000 05240-008 adc output code lsb figure 8. dnl for channel a and channel b 10 ?20 ?15 ?10 ?5 0 5 16000 14000 12000 10000 8000 6000 4000 2000 05240-009 dac output code lsb figure 9. inl performance for channel a and channel b 1.015 0.995 1.000 1.005 1.010 16000 14000 12000 10000 8000 6000 4000 2000 05240-010 adc output code channel a/channel b ratio ?25c +25c +85c figure 10. noncalibrated channel a/channel b ratio
ad9942 rev. a | page 14 of 36 system overview 05240-014 ccd serial interface dout digital image processing asic v driver hd_a, vd_a, hd_b, vd_b cli_a, cli_b v1 > vx, vsg1 > vsgx, subck h1a to h4a, rg_a h1b to h4b, rg_b ad9942 integrated afe + td ccdin_a ccdin_b maximum field dimensions 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max 05240-015 figure 11. typical application figure 12. vertical and horizontal counters figure 11 shows the typical system application diagram for the ad9942. the ccd output is processed by the ad9942 afe circuitry, which consists of a cds, a vga, a clpob, and an adc. the digitized pixel information is sent to the digital image processor chip, where all postprocessing and compression occurs. to operate the ccd, ccd timing param- eters are programmed from the image processor to the ad9942 through the 6-wire serial interface. from the system master clock, cli, which is provided by the image processor, the device generates the high speed ccd clocks and internal afe clocks. all ad9942 clocks are synchronized with vd_x and hd_x. the clpob is programmed and generated internally. the h drivers for h1a to h4a, h1b to h4b, rg_a, and rg_b are included in the ad9942, allowing these clocks to be directly connected to the ccd. an h driver voltage of 3 v is supported in the ad9942. figure 12 shows the horizontal and vertical counter dimensions for the device. all internal horizontal clocking is programmed using these dimensions to specify line and pixel locations. 05240-016 vd_x hd_x cli_x max hd length is 4095 pixels max vd length is 4095 lines figure 13. maximum vd_x/hd_x dimensions
ad9942 rev. a | page 15 of 36 serial interface timing all of the ad9942 internal registers are accessed through a 6-wire serial interface. each register consists of an 8-bit address and a 24-bit data-word. both the 8-bit address and the 24-bit data-word are written starting with the lsb. to write to each register, a 32-bit operation is required, as shown in figure 14 . although many registers are less than 24 bits wide, all 24 bits must be written for each register. if the register is only 16 bits wide, then the upper 8 bits can be filled with 0s during the serial write operation. if fewer than 24 bits are written, the register is not updated with new data. figure 15 shows a more efficient way to write to the registers by using the ad9942 address auto-increment capability. in this method, the lowest desired address is written first, followed by multiple 24-bit data-words. each new 24-bit data-word is written automatically to the next highest register address. by eliminating the need to write each 8-bit address, faster register loading is achieved. the address auto-increment function can be used, starting with any register location, to write to as few as two registers or to as many as the entire register space. 05240-017 sdata _x a0 a1 a2 a4 a5 a6 a7 d0 d1 d2 d3 d21 d22 d23 sck _x sl _x a3 notes 1. x = a, b. 2. individual sdata_x bits are latched upon sck_x rising edges. 3. all 32 bits must be written: 8 bits for address and 24 bits for data. 4. if the register length is <24 bits, then don?t care bits must be usedto complete the 24-bit data length. 5. new data is updated at either the sl_x rising edge or at the hd_x falling edge after the next vd_x falling edge. 6. vd_x/hd_x update position can be delayed to any hd_x falling edge in the field using the update register. vd _x sl updated vd/hd updated hd _x ... ... ... ... ... 8-bit address 24-bit d a t a 1 32 23456789101112 3031 t ls t ds t dh t lh figure 14. serial write operation 05240-018 sdata_x a0 a1 a2 a4 a5 a6 a7 d0 d1 d22 d23 sck_x sl_x a3 notes 1. x = a, b. 2. multiple sequential registers can be loaded continuously. 3. the first (lowest address) register address is written, followed by multiple 24-bit data-words. 4. the address automatically increments with each 24-bit data-word (all 24 bits must be written). 5. sl_x is held low until the last desired register has been loaded. 6. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. d0 d1 d22 d23 d0 ... ... ... data for starting register address data for next register address d2 d1 ... ... ... ... ... ... 1 32 2 3 4 5 6 7 8 9 10 31 3433 56 55 58 57 59 figure 15. continuous serial write operation
ad9942 rev. a | page 16 of 36 complete register listing in table 8 through tabl e 16 , note the following: ? all addresses and default values are expressed in hexadecimal format. ? all registers are vd_x/hd_x updated as shown in figure 14 , except for the registers indicated in table 8 , which are sl_x updated. ? each channel is programmed independently using the 5-wire serial interface. both channels can be programmed with the same register values by tying the sl_a and sl_b signals together and the sdata_a and sdata_b signals together. table 8. updated registers upon rising edge of sl_x register description oprmode afe operation modes ctlmode afe control modes sw_reset software reset bit tgcore _rstb reset bar signal for internal tg core preventupdate prevents update of registers vdhdedge vd/hd active edge fieldval resets internal field pulse hblkretime retimes the hblk to internal clock h1control h1 polarity control rgcontrol rg signal control polarity drvcontrol drive-strength control sampcontrol shp/shd sample control doutphase dout phase control table 9. chn_a and chn_b afe register map address data bit content default (hex) name description 00 [11:0] 4 oprmode afe operation modes (see table 15 ). 01 [9:0] 0 testmode internal test mode. should always be set = 0. 02 [7:0] 80 clamp level clpob level. 03 [11:0] 4 ctlmode afe control modes (see table 16 ). 04 [17:0] 0 testmode test operation only. set = 0. 05 [17:0] 0 testmode test operation only. set = 0. table 10. chn_a and chn_b miscellaneous register map address data bit content default (hex) name description 10 [0] 0 sw_rst software reset.1 = reset all registers to default, then self-clear back to 0. 11 [0] 0 out_control output control. 0 = make all dc outputs inactive. 12 [0] 0 tgcore_rstb timing core reset bar. 0 = reset tg core; 1 = resume operation. 13 [11:0] 0 update serial update. sets the li ne (hd) within the field to update serial data. 14 [0] 0 preventupda te prevents the update of the vd-updated registers. 1 = prevent update. 15 [0] 0 vdhdedge vd/hd active edge. 0 = falling edge triggered; 1 = rising edge triggered. 16 [1:0] 0 fieldval field value sync. 0 = next field 0; 1 = next field 1; 2/3 = next field 2. 17 [0] 0 hblkretime retime hblk to internal h1 clock. pref erred setting is 1. setting to 1 adds one cycle delay to hblk toggle positions. 18 [1:0] 0 test mode internal test mode. should always be set = 0. 19 [0] 0 test mode internal test mode. should always be set = 0. 1a [0] 0 test mode internal test mode. should always be set = 0. e8 [2:0] test mode internal test mode. should always be set = 0. [11:3] 0 vgagain vga gain control.
ad9942 rev. a | page 17 of 36 table 11. chn_a and chn_b clpob register map address data bit content default (hex) name desc ription (the clpobscp0 always starts at line 0) 20 [3:0] f clpobpol start polarities for clpob sequences 0, 1, 2, and 3. 21 [23:0] ffffff clpobtog_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 22 [23:0] ffffff clpobtog_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 23 [23:0] ffffff clpobtog_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 24 [23:0] ffffff clpobtog_3 sequence 3. toggle po sition 1 [11:0] and toggle position 2 [23:12]. 25 [7:0] 00 clpobsptr clpob sequence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6]. 26 [11:0] fff clpobscp1 clpob sequencechange position 1. 27 [11:0] fff clpobscp2 clpob sequencechange position 2. 28 [11:0] fff clpobscp3 clpob sequencechange position 3. table 12. pblk register map address data bit content default (hex) name description (the pblkscp0 always starts at line 0) 30 [3:0] f pblkpol start polarities for pblk sequences 0, 1, 2, and 3. 31 [23:0] ffffff pblktog_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 32 [23:0] ffffff pblktog_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 33 [23:0] ffffff pblktog_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 34 [23:0] ffffff pblktog_3 sequence 3. toggle position 1 [11:0] and toggle position 2 [23:12]. 35 [7:0] 00 pblksptr pblk sequence pointers fo r region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6]. 36 [11:0] fff pblkscp1 pblk sequencechange position 1. 37 [11:0] fff pblkscp2 pblk sequencechange position 2. 38 [11:0] fff pblkscp3 pblk sequencechange position 3. table 13. hblk register map address data bit content default (hex) name description (the hblkscp0 always starts at line 0) 40 [0] 0 testmode test mode. always set = 0 if accessed. 41 [0] 0 testmode test mode. always set = 0 if accessed. 42 [0] 1 testmode test mode. always set = 1 if accessed. 43 [3:0] f hblkmask hblk internal masking polarity. 0 = mask h1 low; 1 = mask h1 high. 44 [23:0] ffffff hblktog12_0 sequence 0. toggle position 1 [11:0] and toggle position 2 [23:12]. 45 [23:0] ffffff hblktog34_0 sequence 0. toggle position 3 [11:0] and toggle position 4 [23:12]. 46 [23:0] ffffff hblktog56_0 sequence 0. toggle position 5 [11:0] and toggle position 6 [23:12]. 47 [23:0] ffffff hblktog12_1 sequence 1. toggle position 1 [11:0] and toggle position 2 [23:12]. 48 [23:0] ffffff hblktog34_1 sequence 1. toggle position 3 [11:0] and toggle position 4 [23:12]. 49 [23:0] ffffff hblktog56_1 sequence 1. toggle position 5 [11:0] and toggle position 6 [23:12]. 4a [23:0] ffffff hblktog12_2 sequence 2. toggle position 1 [11:0] and toggle position 2 [23:12]. 4b [23:0] ffffff hblktog34_2 sequence 2. toggle position 3 [11:0] and toggle position 4 [23:12]. 4c [23:0] ffffff hblktog56_2 sequence 2. toggle position 5 [11:0] and toggle position 6 [23:12]. 4d [23:0] ffffff hblktog12_3 sequence 3. toggle position 1 [11:0] and toggle position 2 [23:12]. 4e [23:0] ffffff hblktog34_3 sequence 3. toggle position 3 [11:0] and toggle position 4 [23:12]. 4f [23:0] ffffff hblktog56_3 sequence 3. toggle position 5 [11:0] and toggle position 6 [23:12]. 50 [7:0] 00 hblksptr hblk sequence pointers for region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6]. 51 [11:0] fff hblkscp1 hblk sequencechange position 1. 52 [11:0] fff hblkscp2 hblk sequencechange position 2. 53 [11:0] fff hblkscp3 hblk sequencechange position 3.
ad9942 rev. a | page 18 of 36 table 14. chn_a and chn_b h1 to h4, rg, shp, shd register map address data bit content default (hex) name description 60 [12:0] 01001 h1control h1 signal control. polarity [0] (0 = inversion; 1 = no inversion). h1 positive edge location [6:1]. h1 negative edge location [12:7]. 61 [12:0] 00801 rgcontrol rg signal control. polarity [0] (0 = inversion; 1 = no inversion). rg positive-edge location [6:1]. rg negative-edge location [12:7]. 62 [14:0] 0 drvcontrol drive-strength control for h1x [2:0], h2x [5:3], h3x [8:6], h4x [11:9], and rg_x [14:12]. drive-current values: 0 = off, 1 = 4.3 ma, 2 = 8.6 ma, 3 = 12.9 ma, 4 = 17.2 ma, 5 = 21.5 ma, 6 = 25.8 ma, 7 = 30.1 ma. 63 [11:0] 00024 sampcontrol shp/shd sample control. shp sampling location [5:0]. shd sampling location [11:6]. 64 [5:0] 0 doutphase dout phase control. table 15. chn_a and chn_b afe operation register detail address data bit content default (hex) name description 00 [1:0] 0 pwrdown 0 = normal operation; 1 = reference standby; 2/3 = total power-down. [2] 1 clpenable 0 = disable clpob; 1 = enable clpob. [3] 0 clpspeed 0 = select normal clpob settling; 1 = select fast clpob settling. [4] 0 fastupdate 0 = ignore vga update; 1 = very fast clamping when vga is updated. [5] 0 pblk_lvl dout value during pblk; 0 = blank to zero; 1 = blank to clamp level. [7:6] 0 test mode internal test mode. should always be set = 3. [8] 0 dcbyp 0 = enable dc restore circuit; 1 = bypass dc restore circuit during pblk. [9] 0 testmode test operation only. set = 0. [11:10] 0 testmode test operation only. set = 0. table 16. chn_a and chn_b afe control register detail address data bit content default (hex) name description 03 [1:0] 0 testmode test operation only. set = 0. [2] 1 testmode test operation only. set = 0. [3] 0 doutdisable 0 = data outputs are driven; 1 = data outputs are three-stated. [4] 0 doutlatch 0 = latch data outputs wi th dout phase; 1 = output latch transparent. [5] 0 grayencode 0 = binary encode da ta outputs; 1 = gray encode data outputs.
ad9942 rev. a | page 19 of 36 channel a and channel b precision timing high speed timing generation the ad9942 generates flexible, high speed timing signals using the precision timing core for both channels. this core is the foundation for generating the timing used for both the ccd and the afe, the reset gate rg_x, the horizontal drivers h1x to h4x, and the shp/shd sample clocks. a unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. timing resolution the precision timing core uses a 1 master clock input (cli) as a reference. this clock should be the same as the ccd pixel clock frequency. figure 16 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. therefore, the edge resolution of the precision timing core is (t cli /48). for more information on using the cli input, see the applications information section. high speed clock programmability figure 17 shows how the high speed clocks, rg_x, h1x to h4x, shp, and shd, are generated. the rg_x pulse has programmable rising and falling edges and can be inverted using the polarity control. the horizontal clock, h1, has programmable rising and falling edges and polarity control. the h2 clock is always the inverse of the h1 clock. table 17 sum- marizes the high speed timing registers and their parameters. each edge location setting is six bits wide, but only 48 valid edge locations are available. therefore, the register values are mapped into four quadrants, wi th each quadrant containing 12 edge locations. table 18 shows the correct register values for the corresponding edge locations. 05240-019 notes 1. pixel clock period is divided into 48 positions, providing fine edge resolution for high speed clocks. 2. there is a fixed delay from the cli_x input to the internal pixel period positions ( t clidly = 6ns typ). p[0] p[48] = p[0] p[12] p[24] p[36] 1 pixel period ... ... cli_x t clidly position figure 16. high speed clock resolution from cli 05240-020 h1x/h3x h2x/h4x ccd signal rg_x 12 3 4 56 programmable clock positions: 1 rg_x rising edge. 2 rg_x falling edge. 3 shp sample location. 4 shd sample location. 5 h1x/h3x rising edge position. 6 h1x/h3x falling edge position (h2x/h4x are inverse of h1x/h3x). figure 17. high speed clock programmable locations
ad9942 rev. a | page 20 of 36 table 17. channel a and channel b h1x to h4x control, rg_x control, drvcontrol, and sampcontrol register parameters parameter length (bit) range description polarity 1 high/low polarity control for h1x and rg_x (0 = no inversion; 1 = inversion). positive edge 6 0 to 47 edge locations positive-edge location for h1x, h3x, and rg_x. negative edge 6 0 to 47 edge locations negative-edge location for h1x and rg_x. sample location 6 0 to 47 sample locati ons sampling location for shp and shd. drive control 3 0 to7 current steps drive current for h1 x to h4x and rg_x outputs, 0 to 7 steps of 4.1 ma each. dout phase 6 0 to 47 edge locations phase locati on of data outputs with respect to pixel period. table 18. channel a and channel b precision timing edge locations quadrant edge location (decimal) register value (decimal) register value (binary) i 0 to 11 0 to 11 000000 to 001011 ii 12 to 23 16 to 27 010000 to 011011 iii 24 to 35 32 to 43 100000 to 101011 iv 36 to 47 48 to 59 110000 to 111011
ad9942 rev. a | page 21 of 36 h driver and rg outputs in addition to the programmable timing positions, the ad9942 features on-chip output drivers for the rg_x and h1x to h4x outputs. these drivers are powerful enough to drive the ccd inputs directly. the h-driver and rg-driver currents can be adjusted for optimum rise and fall time into a particular load by using the drvcontrol register (address 0x62). the drvcontrol register is divided into five 3-bit values, each adjustable in 4.1 ma increments. the minimum setting of 0 is equal to off, or three-state, and the maximum setting of 7 is equal to 30.1 ma. as shown in figure 18 , the h2x/h4x outputs are inverses of h1x. the internal propagation delay resulting from the signal inversion is less than l ns, which is significantly less than the typical rise time driving the ccd load. this results in a h1x/h2x crossover voltage at approximately 50% of the output swing. the crossover voltage is not programmable. digital data outputs the ad9942 data output phase is programmable using the doutphase register (address 0x64). any edge from 0 to 47 can be programmed, as shown in figure 19 . the pipeline delay for the digital data output is shown in figure 20 . 05240-021 fixed crossover voltage h1x/h3x h2x/h4x t pd h2x/h4x h1x/h3x t rise t pd << t rise figure 18. h-clock inverse phase relationship 05240-022 notes 1. digital output data (dout) phase is adjustable with respect to the pixel period. 2. within one clock period, the data transition can be programmed to any of the 48 locations. p[0] p[48] = p[0] cli_x 1 pixel period p[12] p[24] p[36] dout t od figure 19. digital output phase adjustment 05240-023 012345678910111214150123 h-counter reset vd_x notes 1. internal h counter is reset seven cli_x cycles after the hd_x falling edge (when using vdhdedge = 0). 2. typical timing relationship: cli_x rising edge is coincident with hd_x falling edge. hd_x cli_x xx xxx xx h counter (pixel counter) xx x figure 20. pipeline delay for channel a and channel b digital data output
ad9942 rev. a | page 22 of 36 channel a and channel b horizont al clamping and blanking the ad9942 horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. individual sequences are defined for each signal, which are then organized into multiple regions during image readout. this allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts. individual clpob and pblk sequences the afe horizontal timing consists of clpob and pblk, as shown in figure 21 . these two signals are independently programmed using the parameters shown in table 19 . the start polarity, first toggle position, and second toggle position are fully programmable for each signal. the clpob and pblk signals are active low and should be programmed accordingly. up to four individual sequences can be created for each signal. individual hblk sequences the hblk programmable timing, shown in figure 22 , is similar to clpob and pblk. however, there is no start polarity control. only the toggle positions are used to designate the start and stop positions of the blanking period. additionally, there is a polarity control, hblkmask, which designates the polarity of the horizontal clock signal h1 during the blanking period. setting hblkmask high sets h1 low and h2 high during the blanking, as shown in figure 23 . up to four individual sequences are available for hblk. table 19. channel a and channel b clpob and pblk individual sequence parameters parameter length (bit) range description polarity 1 high/low starting polarity of clpob and pblk pulses for sequences 0 to 3. toggle position 1 12 0 to 4095 pixel locations first toggle position within the line for sequences 0 to 3. toggle position 2 12 0 to 4095 pixel locations second toggle position within the line for sequences 0 to 3.
ad9942 rev. a | page 23 of 36 05240-024 3 2 1 hd clpob pblk programmable settings: 1 start polarity (clamp and blank region are active low). 2 first toggle position. 3 second toggle position. active active ... ... figure 21. clpob and pblk pulse placement 05240-025 2 1 hd_x hblk programmable settings: 1 first toggle position = start of blanking. 2 second toggle position = end of blanking. blank blank ... ... figure 22. hblk pulse placement hd_x hblk the polarity of h1 during blanking is programmable (h2 is opposite polarity of h1). h1x/h3x h1x/h3x h2x/h3x ... ... ... ... 05240-026 figure 23. hblk masking control
ad9942 rev. a | page 24 of 36 channel a and channel b special hblk patterns six toggle positions are available for hblk. typically, only two of the toggle positions are used to generate the standard hblk interval. however, the additional toggle positions can be used to generate special hblk patterns, as shown in figure 24 . the pattern in this example uses all six toggle positions to generate two extra groups of pulses during the hblk interval. by changing the toggle positions, different patterns can be created. horizontal sequence control the ad9942 uses sequence change positions (scps) and sequence pointers (sptrs) to organize the individual horizontal sequences. up to four scps are available to divide the readout into four separate regions, as shown in figure 25 . the scp0 is always hard-coded to line 0, and scp1 to scp3 are register programmable. during each region bounded by the scp, the sptr registers designate which sequ ence is used by each signal. clpob, pblk, and hblk each have a separate set of scps. for example, clpobscp1 defines region 0 for clpob, and in that region any of the four clpob sequences can be selected with the clpobsptr register. the next scp defines a new region, in which each signal can be assigned to a different individual se- quence. the sequence control registers are detailed in table 21 . hblk special h-blank pattern is created using multiple hblk toggle positions. h1x/h3x h2x/h4x tog1 tog2 tog3 tog4 tog5 tog6 05240-027 figure 24. generating special hblk patterns up to four individual horizontal clamp and blanking regions may be programmed within a single field, using the sequence change positions. sequence change of position 1 sequence change of position 2 sequence change of position 3 single field (1 vd interval) clamp and pblk sequence region 0 sequence change of position 0 (v counter = 0) clamp and pblk sequence region 3 clamp and pblk sequence region 2 clamp and pblk sequence region 1 05240-028 figure 25. clpob and pblk sequence flexibility
ad9942 rev. a | page 25 of 36 table 20. channel a and channel b hblk individual sequence parameters parameter length (bit) range description hblkmask 1 high/low masking polarity for h1 for sequences 0 to 3 (0 = low; 1 = high). toggle position 1 12 0 to 4095 pixel locations first to ggle position within the line for sequences 0 to 3. toggle position 2 12 0 to 4095 pixel locations second toggle position within the line for sequences 0 to 3. toggle position 3 12 0 to 4095 pixel locations third to ggle position within the line for sequences 0 to 3. toggle position 4 12 0 to 4095 pixel locations fourth toggle position within the line for sequences 0 to 3. toggle position 5 12 0 to 4095 pixel locations fifth toggle position within the line for sequences 0 to 3. toggle position 6 12 0 to 4095 pixel locations sixth to ggle position within the line for sequences 0 to 3. table 21. channel a and channel b horizontal sequence control registers for clpob, pblk, and hblk register length (bit) range description scp 12 0 to 4095 line numbers clpob/pblk/hblk sc p to define horizontal regions 0 to 3. sptr 2 0 to 3 sequence numbers sequence pointer for horizontal regions 0 to 3. table 22. channel a and channel b external hblk register parameters register length (bit) range description hblkdir 1 high/low specifies hblk internally generated or externally supplied. 0 = internal; 1 = external. hblkpol 1 high/low external hblk active polarity. 0 = active low; 1 = active high. hblkextmask 1 high/low external hblk masking polarity. 0 = mask h1 low; 1 = mask h1 high. h-counter synchronization the h-counter reset occurs seven cli cycles after the hd falling edge. 05240-029 012345678910111214150123 h-counter reset vd_x notes 1. internal h counter is reset seven cli_x cycles after the hd_x falling edge (when using vdhdedge = 0). 2. typical timing relationship: cli_x rising edge is coincident with hd_x falling edge. hd_x cli_x xx xxx xx h counter (pixel counter) xx x figure 26. h-counter synchronization
ad9942 rev. a | page 26 of 36 channel a and channel b power-up procedure when the ad9942 is powered up, the following sequence is recommended for channel a and channel b (see figure 27 for each step). 1. turn on the power supplies for the ad9942. 2. apply the master clock input, cli_x, vd_x, and hd_x. 3. although the ad9942 contains an on-chip power-on reset, a software reset of the internal registers is recommended. write a 1 to the sw_rst register (address 0x10), which resets all the internal registers to their default values. this bit is self-clearing and is automatically reset to 0. 4. reset the precision timing core by writing a 0 to the tgcore_rstb register (address 0x12), then write a l to the tgcore_rstb register. this starts the internal timing core operation. 5. write a 1 to the preventupdate register (address 0x14). this prevents an update of the serial register data. 6. write to the desired registers to configure high speed timing and horizontal timing. 7. write a 3 to the [7:6] testmode register (address 0x00). see table 15 . 8. write a 1 to the out_control register (address 0x11). this allows the outputs to become active after the next vd_x/hd_x rising edge. 9. write a 0 to the preventupdate register (address 0x14). this allows the serial information to be updated at the next vd_x/hd_x falling edge. the next vd_x/hd_x falling edge allows register updates, including updates of out_control, to occur which enables all clock outputs. 0 5240-030 vdd (input) serial writes vd_x (output) 1h odd field even field ... ... digital outputs clocks active when out_control register is updated at vd/hd edge h1x/h3x, rg_x h2x/h4x t pwr cli_x (input) hd_x (output) 1v ... ... 1 2 2 3 4 5 6 7 8 9 figure 27. recommended power-up sequence
ad9942 rev. a | page 27 of 36 channel a and channel b analog front end operation the ad9942 signal processing chain is shown in figure 28 . each processing step is essential for achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccdin_x signal to approximately 1.5 v to be compatible with the 3 v supply voltage of the ad9942. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low frequency noise. the timing shown in figure 17 illustrates how the two internally generated cds clocks, shp and shd, are used to sample the reference level and the ccd signal level, respectively. the placement of the shp and shd sampling edges is determined by the setting of the sampcontrol register located at address 0x63. placement of these two clock signals is critical for achieving the best performance from the ccd. 05240-031 ccdin_x digital filter clpob dc restore optical black clamp adc dac 8 cds internal v ref 2v full scale 0db ~ 18db shp shd vga1 1.5v output data latch reft_x refb_x dout phase pblk 1.0v 2.0v dout ad9942 1.0f 1.0f 1.0f vga gain registers clamp level register 14 clpob pblk v-h timing generation shp shd dout phase precision timing generation figure 28. channel a and channel b analog front end functional block diagram
ad9942 rev. a | page 28 of 36 channel a and channel b variable gain amplifier the vga stage provides a gain range of 0 db to 18 db, pro- grammable with 9-bit resolution through the serial digital interface. a minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. the vga gain curve follows a linear-in-db characteristic. the exact vga gain can be calculated for any gain register value by using the equation gain (db) = (0.035 vgagain code ) where the code range is 0 to 511. 20 0 2 4 6 8 10 12 14 16 18 0 50 100 150 200 250 300 350 400 450 500 05240-032 gain code (decimal) gain (db) figure 29. vga gain curve channel a and channel b adc the ad9942 uses a high performance adc architecture, opti- mized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb. the adc uses a 2 v input range. see figure 8 and figure 9 for typical linearity and noise performance plots for the ad9942. channel a and channel b clpob the clpob loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccd black level. during the optical black (ob), or shielded, pixel interval on each line, the adc output is compared with a fixed black level reference, selected by the user in the clamp level register. the value can be programmed between 0 lsb and 255 lsb in 256 steps. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a digital-to-analog converter. typically, the clpob loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during postprocessing, the ad9942 clpob can be disabled using bit d2 in the oprmode register. the clamp level register can be used to provide program- mable offset adjustment even when the loop is disabled. the clpob pulse should be placed during the ccds ob pixel region. it is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. shorter pulse widths can be used, but clamp noise might increase and the ability to track low frequency variations in the black level is reduced. see the channel a and channel b horizontal clamping and blanking section and the applications information section for timing examples. channel a and channel b digital data outputs the ad9942 digital output data is latched using the doutphase register value, as shown in figure 28 . (output data timing is shown in figure 19 and figure 20 .) it is also possible to leave the output latches transparent, so that the data outputs are valid immediately from the adc. programming the afe control register bit d4 to 1 sets the output latches transparent. the data outputs can also be disabled (three-stated) by setting the afe control register bit d3 to 1. the data output coding is typically straight binary, but the coding can be changed to gray coding by setting the afe control register bit d5 to 1.
ad9942 rev. a | page 29 of 36 applications information circuit configuration the ad9942 recommended circuit configuration is shown in figure 30 . achieving good image quality from the ad9942 requires careful attention to the printed circuit board (pcb) layout. all signals should be routed to maintain low noise performance. the ccd_a and ccd_b output signals should be directly routed to pins a1 and a7, respectively, through a 0.1 f capacitor. the master clock, cli_x, should be carefully routed to pins a3 and a9 to minimize interference with the ccdin_x, reft_x, and refb_x signals. the digital outputs and clock inputs should be connected to the digital asic away from the analog and ccd clock signals. placing series resistors close to the digital output pins may help to reduce digital code transition noise. if the digital outputs must drive a load larger than 20 pf, buffering is recommended to minimize additional noise. if the digital asic can accept gray code, the ad9942 outputs can be selected to output data in gray code format using the control register bit d5. gray coding helps reduce potential digital transition noise compared with binary coding. the h1x to h4x and rg_x traces should have low inductance to avoid excessive distortion of the signals. heavier traces are recommended because of the large transient current demand on h1x to h4x from the capacitive load of the ccd. if possible, physically locate the ad9942 closer to the ccd to reduce the inductance on these lines. as always, the routing path should be as direct as possible from the ad9942 to the ccd. the cli_x and ccdin_x pcb traces should be carefully matched in length and impedance to achieve optimal channel- to-channel matching performance. grounding/decoupling recommendations as figure 30 shows, a single ground plane is recommended for the ad9942. this ground plane should be as continuous as possible, particularly around the p-, ai-, and a-type pins, to ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all high frequency decoupling capacitors should be located as close as possible to the package pins. all the supply pins must be decoupled to ground with good quality, high frequency chip capacitors. there should also be a 4.7 f or larger bypass capacitor for each main supplythat is, the avdd_x, rgvdd_x, hvdd_x, and drvdd_x although this is not necessary for each individual pin. in most applications, it is easier to share the supply for rgvdd_x and hvdd_x, which can be done as long as the individual supply pins are separately bypassed. a separate 3 v supply can be used for drvdd_x, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. a separate ground for drvss_x is not recommended. the reference bypass pins (reft_x, refb_x) should be decoupled to ground as close as po ssible to their respective pins. the analog input capacitor (ccdin_x) should also be located close to the pin. the gnd connections should be tied to the lowest impedance ground plane on the pcb. performance does not degrade if several of these gnd connections are left unconnected for routing purposes.
ad9942 rev. a | page 30 of 36 a1 ccdin_a d1 refb_a c1 reft_a b2 sl_a c2 sdata_a d2 sck_a e1 hd_a e2 vd_a e4 hvdd_a e3 hvss_a f4 h1a f3 h2a d4 h3a d3 h4a f1 dvdd_a f2 dvss_a g1 d0_a (lsb) h1 d1_a j1 d2_a k1 d3_a g2 d4_a h2 d5_a k2 d6_a g3 d7_a h3 d8_a b7 avss_b a7 ccdin_b d7 refb_b c7 reft_b b8 sl_b c8 sdata_b d8 sck_b e7 hd_b e8 vd_b e10 hvdd_b e9 hvss_b f10 h1b f9 h2b d10 h3b d9 h4b f7 dvdd_b f8 dvss_b g7 d0_b (lsb) h7 d1_b j7 d2_b k7 d3_b g8 d4_b h8 d5_b k8 d6_b g9 d7_b j3 d9_a k4 d10_a j4 d11_a h4 d12_a g4 d13_a (msb) k3 drvdd_a j2 drvss_a f5 gnd g5 gnd h5 gnd j5 gnd k5 gnd k6 gnd j6 gnd h6 gnd g6 gnd f6 gnd j8 drvss_b k9 drvdd_b g10 d13_b (msb) h10 d12_b j10 d11_b k10 d10_b j9 d9_b h9 d8_b b1 avss_a a2 avdd_a a3 cli_a c3 rgvss_a c4 rgvdd_a b4 rg_a a4 tcvdd_a b3 tcvss_a a5 gnd b5 gnd c5 gnd d5 gnd e5 gnd e6 gnd d6 gnd c6 gnd b6 gnd a6 gnd b9 tcvss_b a10 tcvdd_b b10 rg_b c10 rgvdd_b c9 rgvss_b a9 cli_b a8 avdd_b ad9942 0.1f 3v analog supply 4.7f 0.1f h1a to h4 a driver supply h1a to h4a outputs chn_a ccd signal vd common input hd common input serial interface for chn_a 4.7f 4.7f + + 3v driver 3v driver 4 1.0f 1.0f 0.1f 0.1f 3v analog supply 0.1f h1b to h4b driver supply h1b to h4b outputs chn_b ccd signal vd common input hd common input serial interface for chn_b 4.7f 4 1.0f 1.0f 0.1f chn_a data outputs 14 chn_b data outputs 14 0.1f 0.1f 3 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 4.7f + rg_b driver supply rg_b output 3v analog supply + 4.7f common master clock input 3v analog supply rg_a driver supply rg_a output 3v analog supply + 4.7f + 4.7f 3v analog supply common master clock input 05240-033 figure 30. recommended circuit configuration
ad9942 rev. a | page 31 of 36 driving the cli input the ad9942 cli can be used in two configurations, depending on the application. figure 31 shows a typical dc-coupled input from the master clock source. when the dc-coupled technique is used, the master clock signal should be at standard 3 v cmos logic levels. as shown in figure 32 , a 1000 pf ac coupling capacitor can be used between the clock source and the cli input. in this configuration, the cli input performs a self-bias to the proper dc voltage level of approximately 1.4 v. when the ac- coupled technique is used, the master clock signal can be as low as 500 mv in amplitude. horizontal timing sequence example figure 33 shows an example ccd configuration. the horizontal register contains 28 dummy pixels, which occur on each line clocked from the ccd. in the vertical direction, there are 10 ob lines at the front of the readout and 2 at the back of the readout. the horizontal direction has 4 ob pixels in the front and 48 in the back. to configure the ad9942 horizontal signals for this ccd, three sequences can be used. figure 34 shows the first sequence to be used during vertical blanking. during this time, there are no valid ob pixels from the sensor, so the clpob signal is not used. pblk can be enabled during this time because no valid data is available. figure 35 shows the recommended sequence for the vertical ob interval. the clamp signals are used across the whole lines to stabilize the clamp loop of the ad9942. figure 36 shows the recommended sequence for the effective pixel readout. the 48 ob pixels at the end of each line are used for the clpob signal. 05240-034 cli_x ad9942 asic master clock figure 31. cli connection, dc-coupled 05240-035 lpf 1nf cli_x ad9942 asic master clock figure 32. cli connection, ac-coupled 05240-036 v h use sequence 2 use sequence 3 sequence 2 (optional) horizontal ccd register effective image area 2 8 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines figure 33. example ccd configuration
ad9942 rev. a | page 32 of 36 vertical shift vert shift sequence 1: vertical blanking lines ccdin shp shd h1x/h3x h2x/h4x hblk clpob dummy invalid pixels invalid pix 05240-037 figure 34. horizontal sequence during vertical blanking vertical shift v ert shif t sequence 2: vertical optical black lines ccdin shp shd h1x/h3x h2x/h4x hblk clpob optical black dummy optical black 05240-038 figure 35. horizontal sequences during vertical ob pixels vertical shift vert shift sequence 3: effective pixel lines ccdin shp shd h1x/h3x h2x/h4x hblk clpob optical black optical black dummy effective pixels optical black 05240-039 figure 36. horizontal sequences during effective pixels
ad9942 rev. a | page 33 of 36 outline dimensions b c d e f g h j k a seating plane 0.25 min detail a 0.55 0.50 0.45 ball diameter coplanarity 0.12 0.80 bsc 7.20 bsc sq 10987654321 top view ball a1 pad corner detail a 1.40 ma x 0.65 min a1 corner index area 9.10 9.00 sq 8.90 compliant to jedec standards mo-205-ab. figure 37. 100-lead chip scale package ball grid array [csp_bga] (bc-100-1) dimensions shown in millimeters ordering guide model temperature range package description package option ad9942bbcz 1 ?25c to +85c 100-lead chip scale package ball grid array [csp_bga] bc-100-1 AD9942BBCZRL 1 ?25c to +85c 100-lead chip scale package ball grid array [csp_bga] bc-100-1 1 z = pb-free part.
ad9942 rev. a | page 34 of 36 notes
ad9942 rev. a | page 35 of 36 notes
ad9942 rev. a | page 36 of 36 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05240-0-8/06(a)

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